1. Field of the Invention
This present invention relates to an automatic sampling clock generation system; it is especially about a clock generation system for automatically generating a sampling signal and a holding signal to an analog front end circuit.
2. Description of the Prior Art
Because the outputting signal of general image sensors periodically contains a level signal and a reference signal, an analog front end circuit usually utilizes the format of the correlated double sampling to sample the outputting signal of the image sensor; it also amplifies and transforms the result into a digital signal for the follow-up element processing.
Referring to the system shown in FIG. 1, FIG. 1 is a working diagram of a sensor outputting signal 10, a sampling clock signal 11, and a holding clock signal 13 of the prior art. Sensor outputting signal 10 of the sensor periodically includes a reference signal 12 and an level signal 14. Due to the fact that the reference signal 12 and level signal 14 are not considerably smooth, it includes a transition state Ta, Tb and a steady state Sa, Sb; because it can only sample the reference signal 12 and level signal 14 in the steady state Sa, Sb, the available part for sampling is considerably narrow. In the prior art, in order to avoid having sampling errors, the location of sampling work must be distant from the transition state Ta, Tb; usually, half of the width of the steady state Sa of the reference signal 12 is taken as the duty cycle A of the sampling clock signal 11, and half of the width of the steady state Sb of the level signal 14 is taken as the duty cycle B of the holding clock signal 13. Therefore, the width of the duty cycle A of the sampling clock signal 11 and the duty cycle B of the holding clock signal 13 are very narrow.
In addition, the synchronization state of the sampling clock signal 11 or the holding clock signal 13 and the sensor outputting signal 10 also affects the quality of the sampling work; if the steady states Sa of the sampling clock signal 11 and the reference signal 12 are not synchronized, or if the holding clock signal and the level signal 14 are not synchronized, it will result in sampling errors and will affect the quality of the image.
The analog front end circuit of the prior art utilizes a register to store the adjusting finish parameter used in the process of producing terminal products (e.g. digital camera, digital video camera); the parameter controls a delay lock loop to suitably generate the sampling clock signal 11 and holding clock signal 13. However, the register can only store the invariable parameter; when there are changed in the external environmental factors, such as temperature, humidity, or voltage, these changes may cause errors in the sensor outputting signal 10, the sampling clock signal 11, and the holding clock signal 13 that were outputted by the sensor, and it may even cause an asynchronous situation. Therefore, the analog front end circuit of the prior art can not accurately adjust the sampling clock signal 11 and the holding clock signal 13 as errors in signal sampling may occur, and the quality of the image may be affected.
Moreover, as there are increasing demands in the function requirements of an image collecting apparatus, such as 4 continuous shootings in high speed, 8 continuous shootings, even multiple continuous shootings in much higher speed, and the function of shutter chance, in order to accelerate the speed of the image data processing to increase the number of processing data of a unit time, it will probably satisfy the requirement by shortening the width of the steady state Sa of the reference signal 12 and the steady state Sb of the level signal 14. Therefore, it makes the synchronism request of the sampling clock signal 11, the holding clock signal 13, and the sensor outputting signal 10 more strict and demanding.
Therefore, the main objective of this invention is to provide an automatic sampling clock generation system and method to overcome the above problems.